A continuing trend in the semiconductor industry is to decrease chip size while increasing the density of components per unit area. This has lead to a decrease in the linewidth of both conductors and the spaces between the conductors, making it advantageous to use several layers of conductors, typically formed of metal for the uppermost conductor levels, in the integrated circuit device. Because of the increase in the number of metallization layers it has become important that the interlevel dielectric structures that serve as insulators between adjacent metallization layers are as planar as possible. To produce planar interlevel dielectric structures the thickness of the interlevel dielectric structures must be increased. Additionally, increases in the thickness of the interlevel dielectric structures also reduce the interlevel capacitance, which has a positive effect on the speed of the circuit. However, the increase in the thickness of the interlevel dielectric structures poses problems for via etch and plug formation.
FIG. 1, is a cross-sectional view of conventionally formed vias 22, 24, and plugs 28, 30, with thin barriers 26, 27 on the sidewalls and bottoms of the vias, formed in a thick interlevel dielectric structure 32. The interlevel dielectric structure 32 is made up of a first dielectric layer 46 deposited over conductive elements 12, 14 and an insulation layer 44; a planarizing layer 48; and a thick second dielectric 20.
As the thickness of the interlevel dielectric structure increases or the device size decreases the aspect ratios of the vias formed in the interlevel dielectric structure increases. Referring to FIG. 1, the aspect ratios of vias 22, 24 is the ratio of the height of the vias to the widths of the vias. The vias 22, 24 have to allow contact plugs 28, 30 and barrier layers 26, 27 to make contact between the conductive elements 12, 14 of the metallization layer below and the enclosures 34, 36 above the interlevel dielectric structure 32, so the vias must extend through the entire interlevel dielectric structure 32. For vias etched through the entire interlevel dielectric structure, the heights of the vias 34, 36 is the thickness of the interlevel dielectric structure 32. Therefore, as the thickness of the interlevel dielectric structure increases, the heights of the vias increase, causing an increase in the aspect ratios of the vias. Additionally, the widths of the vias 22, 24 cannot exceed the widths of the conductive elements 12, 14 over which the vias are formed. Therefore, as the device size decreases, causing the widths of the conductive elements to decrease, the widths of the vias 22, 24 must decrease, and again the aspect ratios of the vias 22, 24 increase.
As the aspect ratios of the vias 22, 24 increase, the ease of etching these vias decrease, particularly as the aspect ratios increase significantly above 1. In vias 22, 24 with high aspect ratios, it is difficult to get a vertical etch, resulting in slanted sidewalls. The slanted sidewalls of the vias 22, 24 cause problems with producing uniform barriers 26, 27 in the vias 22, 24. The slanted sidewalls also make the tops of the vias 22, 24 larger than the bottoms of the vias. To compensate for this, either the width of the top of the vias 22, 24 will be larger than the width of the conductive elements 12, 14 below the vias and the enclosures 34, 36 above the via, or the size of the entire vias 22, 24 must be reduced.
In vias, like via 24, where the width of the top of a via 24 is larger than the enclosure 36 above the via the contact plug 30 and barrier 27 will not be entirely covered by the enclosure 36, part of the barrier 27 may be etched away in later process steps, reducing the reliability of the device. Additionally, larger tops of vias increase the misalignment sensitivity of the enclosures, even if the enclosure is larger than the top of the via, as in the case of enclosure 34 and via 22. Although the enclosure 34 is large enough to cover the entire top of the via 22, any misalignment of the enclosure 34 will result in the barrier 26 and plug 28 not being entirely covered by the top of the via, producing the problems discussed above. If one were to enlarge the enclosures 34, 36 to ensure that they cover the vias 22, 24 entirely, a short circuit may result because of the small distance between conductors.
Furthermore, the widths of the contact plugs 28, 30 at the tops of the vias will also be large. Contact plugs are usually either tungsten or aluminum. Tungsten is typically the metal used to fill vias with high aspect ratio since tungsten has better flow properties than aluminum. Contact plugs 28, 30 are typically formed by depositing tungsten and etching it back to leave tungsten only in the vias. However, because of the widths of the tops of the vias 22, 24 the tungsten does not etch evenly and gaps 23a, 23b, 25a, 25b are formed at the tops of the vias, which reduce the performance and reliability of the device. The thickness of the tungsten in the vias can also cause cracks 19 in the tungsten.
The smaller bottoms of vias 22, 24 also make it more difficult for the metal of the plug to fill the vias, resulting in poor step coverage. For larger sized vias, like via 24, this can cause gaps at the bottom of the via which lead to reduced performance and reliability of the device. For vias, like via 22, where the entire size of the via is reduced, the poor step coverage can result in a void 21 the width of the bottom the via, which produces an open circuit.
It is therefore an object of this invention to provide a method of forming vias with low aspect ratios in thick interlevel dielectric structures.
It is further an object of this invention to provide a method of forming vias with aspect ratios of about 1 or below in thick interlevel dielectric structures.
It is further an object of this invention to provide a method of forming vias such that the enclosure sensitivity of the conductors above the vias is reduced.
It is further an object of this invention to provide a method of forming vias with straight sidewalls.
It is further an object of this invention to provide a method of forming contact plugs with good step coverage.
It is further an object of this invention to provide such a method that utilizes conventional process flows.
It is further an object of the present invention to provide integrated circuit formed according to such a method.
Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.